Clock Positive Width Definition

Clock Positive Width is defined as the time difference between a rising edge and the following falling edge in a clock cycle. Clock positive width is also the time period during which the clock signal remains above the threshold reference level in a clock period.

Clock Positive Width DspSee Symbol

Active Edge	Clock Positive Width
Not Applicable	Clock Positive Width is the time difference between a rising edge and the following falling edge in a clock cycle.

Significance of statistics:
Mean	The mean positive width should be ideally equal to the half of clock period. Any deviation will result in either a smaller setup or a smaller hold time. In a DDR system, it will affect both the setup & hold times.
Min	The min positive width should be ideally equal to the half of clock period. A smaller value will result in a smaller hold time in active rising edge systems or a smaller setup time in active falling edge systems.
Max	The max positive width should be ideally equal to the half of clock period. A higher value will result in a smaller setup time in active rising edge systems or a smaller hold time in active falling edge systems.
Peak cy-cy	Very important. The peak cycle-to-cycle value should be as small as possible. Any value greater than zero will result in jitter and reduction in timing margin.
Peak-to-peak	The peak-to-peak value should be as small as possible. Any value greater than zero will result in reduction in timing margin.

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Jitter & Timing Measurement/Analysis Software