Clock Positive Duty Cycle Definition

Clock Positive Duty Cycle is defined as the ratio of clock positive width to the clock period expressed as a percentage in a given clock cycle. Clock positive duty cycle can range from 0% to 100%. The sum of positive duty cycle and negative duty cycle is always 100%.

Clock Positive Duty Cycle DspSee Symbol

Active Edge	Clock Positive Duty Cycle
Falling	Falling edge Clock Positive Duty Cycle is the positive width as a percentage of period in a given clock cycle. It varies from 0% to 100%. The period in this case is measured from falling edge to falling edge.
Rising	Same as above except that the period in this case is measured from rising edge to rising edge.
Both	Not Applicable.

Significance of statistics:
Mean	The mean positive duty cycle should be ideally equal to 50%. Any deviation will result in either a smaller setup or a smaller hold time. In a DDR system, it will affect both the setup & hold times.
Min	The min positive duty cycle should be ideally equal to 50%. A smaller value will result in a smaller hold time in active rising edge systems or a smaller setup time in active falling edge systems.
Max	The max positive duty cycle should be ideally equal to 50%. A higher value will result in a smaller setup time in active rising edge systems or a smaller hold time in active falling edge systems.
Peak cy-cy	Very important. The peak cycle-to-cycle value should be as small as possible. Any value greater than zero will result in jitter and reduction in timing margin.
Peak-to-peak	The peak-to-peak value should be as small as possible. Any value greater than zero will result in reduction in timing margin.

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