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JitLab

Meas Definitions


 

Clock Positive Cycle-Cycle Duty Cycle Definition


DspSee Symbol symbol measure clock positive cycle-cycle duty cycle


Active Edge Clock Positive Cycle-Cycle Duty Cycle
Falling It is the time difference between two consecutive positive duty cycle measurements.
Rising - do -
Both Not Applicable

Significance of statistics:
MeanVery important for DDR and dual-strobe systems. A higher mean positive cycle-to-cycle duty cycle will directly result in reduction of timing margins.
MinNot important.
MaxVery important for DDR and dual-strobe systems. A higher max positive cycle-to-cycle duty cycle will directly result in reduction of timing margins.
Peak cy-cyGood for understanding the jitter distribution in DDR and dual-strobe systems.
Peak-to-peakGood for understanding the jitter distribution in DDR and dual-strobe systems.


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